In very large scale integration (VLSI) circuit design, one challenge is to control the arrival times of critical signals according to certain arrival time relationship constraints. For example, in SRAM, a pre-charge signal should be turned off before turning on a write enable signal. As technology improves and VLSI designs advance, the arrival-time issue becomes even more challenging, due to increasing circuit nonlinearities and tighter timing constraints. Additionally, large scaled manufacturing introduces variations across process, voltage, and temperature (PVT) corners. These variations impact critical signal timing and skew “worst case” timing margins.
Another complicating factor is the increasing prevalence of multi-power-domain designs, which are often found in mobile computing. Single-power-domain designs tend to consume more power than multi-power-domain equivalents, making the multi-power-domain circuits more amenable to mobile applications. However, lower voltage levels are typically slower than higher voltage levels. For example, in SRAM, where logic levels are lower than cell voltages, delay chains for the logic level signals, such as pre-charge, must be shorter than delay chains for the cell voltage signals, such as the wordline.
One approach to managing arrival times of critical signals is to introduce a fixed margin, or delay, that accommodates the worst case latency in a particular signal path. Fixed margins tend to be overly conservative over a majority of the PVT domain and ultimately introduce performance penalties on the system. Alternatively, multiple delay paths can be multiplexed such that different delay paths can be utilized under different scenarios. This approach reduces system performance penalties, however, it also consumes more area.